This invention relates to semiconductor memory devices and more particularly to the configuration of SRAM memory devices. 2. Description of Related Art
Mechanical stress has been a problem which has existed in Shallow Trench Isolation (STI) technology. Mechanical stress tends to induce crystal defects which will result in creating leakage paths. It is necessary that such leakage paths should be suppressed to improve yield.
In U.S. Pat. No. 5,466,632 of Lur et al. a FOX region with curvilinear boundaries is employed to reduce stress.
In accordance with this invention, 90 degree transitions are employed at critical locations, while using 45 degree transition as few times as possible, where STI technology is used in an SRAM layout.
Problems which are solved by the present invention are as follows:
1. Leakage is decreased by reduction of crystal defects.
2. Large contact (CO)/active area (AA) extension reduces the difficulties associated with photolithographic misalignment.
3. The contact etch window is increased because no stop layer (such as a silicon nitride stop layer) is required to be employed.
In accordance with this invention, a method of forming a layout for an SRAM device is provided having doped regions including a source region, a drain region, and active areas, a wordline conductor and contacts. First form a layout of at least one source/drain region in a doped semiconductor substrate with 90xc2x0 transitions in critical locations where a source/drain region is to be formed; form a dielectric layer above the active areas; form the wordline conductor above the active areas transverse to the active areas, and form source regions in the critical locations in the active areas juxtaposed with the wordline conductor to form pass gate transistors while simultaneously forming drain regions in the active areas juxtaposed with the wordline conductor on the opposite side from the source regions to form pass gate transistors, forming the sidewalls along the  less than 100 greater than  crystal plane. Then, form the contacts to the source/drain regions formed between the wordline conductor extending down through to the dielectric layer to the source/drain regions. Substrate stress is reduced because the large active area region formed in the substrate assures that the contacts are formed on the  less than 100 greater than  surfaces of the mesas are in contact with the mesas formed on the substrate and that the  less than 110 greater than  surfaces of the silicon of the mesas are shielded from the contacts.
In accordance with another aspect of this invention, an SRAM device with a preferred layout having source regions, drain regions, active areas, a wordline conductor and contacts. Regions are formed in a doped silicon semiconductor substrate with 90xc2x0 transitions in critical locations where source regions are to be formed. A dielectric layer is formed above the active areas. The wordline conductor is composed of doped polysilicon formed above the active areas transverse to the active areas. Source regions are formed in the critical locations in the active areas juxtaposed with the wordline conductor to form pass gate transistors while simultaneously formed drain regions in the active areas juxtaposed with the wordline conductor on the opposite side from the source regions to form pass gate transistors. The source region sidewalls are formed along the  less than 100 greater than  crystal plane. The contacts to the drain regions formed between the wordline conductor extending down through to the dielectric layer to the drain regions. The source regions and the drain regions have similar sizes and shapes. Once again, substrate stress is reduced because the large active area region formed in the substrate assures that the contacts are formed on the  less than 100 greater than  surfaces of the mesas are in contact with the mesas formed on the substrate and that the  less than 110 greater than  surfaces of the silicon of the mesas are shielded from the contacts.